1. Field of the Invention
The present invention relates to a semiconductor device which includes a FD(fully-depleted) MOSFET(Metal Oxide Semiconductor Field Effect Transistor) and a PD(partially-depleted) MOSFET in a common SOI(Silicon On Insulator) substrate.
2. Description of the Related Art
A semiconductor device that has a FD-MOSFET and a PD-MOSFET formed in the common SOI layer is described in the following references.
Japanese Patent Publication Laid-Open No. Hei 9(1997)-135030
Japanese Patent Publication Laid-Open No. Hei 11(1999)-298001
The references describe an SOI device that has a FD-MOSFET and a PD-MOSFET in the common silicon layer formed in the SOI substrate.
However, in order to shrink a size of elements formed in the silicon layer, the silicon layer becomes thin. Therefore, a variation of the thickness of the silicon layer at a channel region of the MOSFET is increased. Further, a variation of an electrical characteristic of the MOSFET formed in the silicon layer is increased.
(1) A SOI substrate has a variation of thickness that is formed during a manufacturing process.
(2) A magnitude of the variation of the silicon layer does not depend on a total thickness of the silicon layer. When the silicon layer becomes thin, the ratio of the magnitude of the variation increases. For example, an average of the thickness of the silicon layer is 100 nm and the variation of the silicon layer is ±2 nm, the ratio of the magnitude of the variation is ±2/100=±0.02. If an average of the thickness of the silicon layer is 50 nm, the variation of the silicon layer is ±2 nm. That is, the ratio of the magnitude of the variation increases ±2/50=±0.04.
(3) When the MOSFET is formed in the silicon layer of the SOI substrate, an electrical characteristic of the MOSFET is related to the thickness of the silicon layer. That is, when the silicon layer becomes thin, the variation of the electrical characteristic of the MOSFET is increased